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cy23ep09 2.5 v or 3.3 v, 10-220 mhz, low jitter, 9-output zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07760 rev. *c revised june 1, 2011 features 10 mhz to 220 mhz maximum operating range zero input-output propagation delay, adjustable by loading on clkout pin multiple low-skew outputs ? 45 ps typical output-output skew ? one input drives nine outputs, grouped as 4 + 4 + 1 25 ps typical cycle-to-cycle jitter 15 ps typical period jitter standard and high dr ive strength options available in space-saving 16-pin 150-mil small outline integrated circuit (soic) or 4. 4-mm thin shrunk small outline package (tssop) packages 3.3 v or 2.5 v operation industrial temperature available functional description the cy23ep09 is a 2.5 v or 3.3 v zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin soic or tssop package. the -1h version operates up to 220 (200) mhz frequencies at 3.3 v (2.5 v), and has higher drive than the -1 devices. all parts have on-chip plls that lock to an input clock on the ref pin. the phase-locked loop (pll) feedback is on-chip and is obtained from the clkout pad. there are two banks of four outputs each, which can be controlled by the select inputs as shown in the ?select input decoding? table on page 4. if al l output clocks are not required, bankb can be three-stated. the select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. the pll enters a power-down mode when there are no rising edges on the ref input (less than ~2 mhz). in this state, the outputs are three-stated and the pll is turned off, resulting in less than 25 ? a of current draw. in the special case when s2:s1 is 1:0, the pll is bypassed and ref is output from dc to the maximum allowable frequency. the part behaves like a non-zero delay buffer in this mode, and the outputs are not tri-stated. the cy23ep09 is available in different configurations, as shown in the ordering information table. the cy23ep09-1 is the base part. the cy23ep09-1h is the high-drive version of the -1, and its rise and fall times are much faster than the -1. these parts are not intended for 5 v input-tolerant applications block diagram pll mux select input ref s2 s1 clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 decoding clkout [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 2 of 17 contents pin configuration ............................................................. 3 pin definition .................................................................... 4 select input decoding ...................................................... 4 zero delay and skew control .......................................... 4 absolute maximum conditions ....................................... 5 operating conditions ....................................................... 5 3.3 v dc electrical specifications ................................... 5 2.5 v dc electrical specifications ................................... 6 3.3 v and 2.5 v ac electrical specifications .................. 6 switching waveforms ...................................................... 8 test circuits ...................................................................... 8 supplemental parametric information ............................ 9 ordering code definition .... ....................................... 13 package drawing and dimensions ............................... 14 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17 [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 3 of 17 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ref clka1 clka2 v dd gnd clkb1 clkb2 s2 clkout clka4 clka3 v dd gnd clkb4 clkb3 s1 top view [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 4 of 17 zero delay and skew control all outputs should be uniformly loaded to achieve zero delay between the input and output. since the clkout pin is the internal feedback to the pll, its relative loading can adjust the input-output delay. the output driving the clkout pi n will be driving a total load of 5 pf plus any additional load externally connected to this pin. for applications requiring zero input-output delay, the total load on each output pin (including clkout) must be the same. if input-output delay adjustments are required, the clkout load may be changed to vary the delay between the ref input and remaining outputs. for zero output-output skew, be sure to load all outputs equally. for further information refer to the application note entitled ?cy2305 and cy2309 as pci and sdram buffers?. notes 1. weak pull-down. 2. weak pull-down on all outputs. 3. weak pull-ups on these inputs. 4. this output is driven and has an internal feedback for the pll. the load on this output can be adjusted to change the skew be tween the reference and output. pin definition pin signal description 1ref [1] input reference frequency 2 clka1 [2] buffered clock output, bank a 3 clka2 [2] buffered clock output, bank a 4v dd 3.3 v or 2.5 v supply 5 gnd ground 6 clkb1 [2] buffered clock output, bank b 7 clkb2 [2] buffered clock output, bank b 8s2 [3] select input, bit 2 9s1 [3] select input, bit 1 10 clkb3 [2] buffered clock output, bank b 11 clkb4 [2] buffered clock output, bank b 12 gnd ground 13 v dd 3.3 v or 2.5 v supply 14 clka3 [2] buffered clock output, bank a 15 clka4 [2] buffered clock output, bank a 16 clkout [2] buffered output, internal feedback on this pin select input decoding s2 s1 clock a1?a4 clock b1?b4 clkout [4] output source pll shutdown 0 0 three-state three-state driven pll n 0 1 driven three-state driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 5 of 17 absolute maximum conditions supply voltage to ground potential .................?0.5 v to 4.6 v dc input voltage .....................................v ss ? 0.5 v to 4.6 v storage temperature................................... ?65 c to 150 c junction temperature.................................................. 150 c static discharge voltage (per mil-std-883, method 3015... .............. ............ > 2000 v operating conditions parameter description min max unit v dd3.3 3.3 v supply voltage 3.0 3.6 v v dd2.5 2.5 v supply voltage 2.3 2.7 v t a operating temperature (ambient temperature)?commercial 0 70 c operating temperature (ambient temperature)?industrial ?40 85 c c l [5] load capacitance, <100 mhz, 3.3 v ? 30 pf load capacitance, <100 mh z, 2.5 v with high drive ? 30 pf load capacitance, <133.3 mhz, 3.3 v ? 22 pf load capacitance, <133.3 mhz, 2.5 v with high drive ? 22 pf load capacitance, <133.3 mhz, 2.5 v with standard drive ? 15 pf load capacitance, >133.3 mhz, 3.3 v ? 15 pf load capacitance, >133.3 mhz, 2.5 v with high drive ? 15 pf c in input capacitance [6] ?5pf bw closed-loop bandwidth (typical), 3.3 v 1?1.5 mhz closed-loop bandwidth (typical), 2.5 v 0.8 mhz r out output impedance (typical ), 3.3 v high drive 29 ? output impedance (typical), 3.3 v standard drive 41 ? output impedance (typical ), 2.5 v high drive 37 ? output impedance (typical), 2.5 v standard drive 41 ? t pu power-up time for all vdd?s to reach minimum specified voltage (power ramps must be monotonic) 0.01 50 ms theta ja [7] dissipation, junction to ambient, 16-pin soic 95 c/w dissipation, junction to am bient, 16-pin tssop 70 c/w theta jc [7] dissipation, junction to case, 16-pin soic 58 c/w dissipation, junction to case, 16-pin tssop 48 c/w 3.3 v dc electrical specifications parameter description test conditions min max unit v dd supply voltage 3.0 3.6 v v il input low voltage ? 0.8 v v ih input high voltage 2.0 v dd +0.3 v i il input leakage current 0 < v in < v il ?10 ? a i ih input high current v in = v dd ?100 ? a v ol output low voltage i ol = 8 ma (standard drive) i ol = 12 ma (high drive) ? ? 0.4 0.4 v v v oh output high voltage i oh = ?8 ma (standard drive) i oh = ?12 ma (high drive) 2.4 2.4 ? ? v v i dd (pd mode) power down supply current ref = 0 mhz (commercial) ? 12 ? a ref = 0 mhz (industrial) ? 25 ? a i dd supply current unloaded outputs, 66-mhz ref ? 30 ma notes 5. applies to test circuit #1. 6. applies to both ref clock and internal feedback path on clkout. 7. theta ja, eia jedec 51 test board conditions, 2s2p; theta jc mil-spec 883e method 1012.1. [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 6 of 17 2.5 v dc electrical specifications parameter description test conditions min max unit v dd supply voltage 2.3 2.7 v v il input low voltage ? 0.7 v v ih input highvoltage 1.7 v dd + 0.3 v i il input leakage current 0133.3 mhz 40 ? 60 % t 2 ?? t 1 output duty cycle [9] <133.3 mhz 47 ? 53 % >133.3 mhz 45 ? 55 % t 3, t 4 rise, fall time (3.3v) [9] std drive, cl = 30 pf, <100 mhz ? ? 1.6 ns std drive, cl = 22 pf, <133.3 mhz ? ? 1.6 ns std drive, cl = 15 pf, <167 mhz ? ? 0.6 ns high drive, cl = 30 pf, <100 mhz ? ? 1.2 ns high drive, cl = 22 pf, <133.3 mhz ? ? 1.2 ns high drive, cl = 15 pf, >133.3 mhz ? ? 0.5 ns t 3, t 4 rise, fall time (2.5 v) [9] std drive, cl = 15 pf, <133.33 mhz ? ? 1.5 ns high drive, cl = 30 pf, <100 mhz ? ? 2.1 ns high drive, cl = 22 pf, <133.3 mhz ? ? 1.3 ns high drive, cl = 15 pf, >133.3 mhz ? ? 1.2 ns t 5 output to output skew [9] all outputs equally loaded, 3.3 v supply, 2.5 supply standard drive ? 45 100 ps all outputs equally loaded, 2.5 v supply high drive ? ? 110 ps t 6 delay, ref rising edge to clkout rising edge [9] pll bypass mode 1.5 ? 4.4 ns pll enabled @ 3.3 v ?100 ? 100 ps pll enabled @2.5 v ?200 ? 200 ps notes 8. for the given maximum loading conditions. see c l in operating conditions table. 9. parameter is guaranteed by design and char acterization. not 100% tested in production. [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 7 of 17 t 7 part to part skew [10] measured at v dd /2. any output to any output, 3.3 v supply ? ? 150 ps measured at v dd /2. any output to any output, 2.5 v supply ? ? 300 ps t lock pll lock time [10] stable power supply, valid clocks presented on ref and clkout pins ??1.0ms t jcc [10,11] cycle-to-cycle jitter, peak 3.3 v supply, >66 mhz, <15 pf ? 25 55 ps 3.3 v supply, >66 mhz, <30 pf, standard drive ? 65 125 ps 3.3 v supply, >66 mhz, <30 pf, high drive ? 53 100 ps 2.5 v supply, >66 mhz, <15 pf, standard drive ? 35 95 ps 2.5 v supply, >66 mhz, <15 pf, high drive ? 30 65 ps 2.5 v supply, >66 mhz, <30 pf, high drive ? 75 145 ps s2:s1 = 1:0 mode, 3.3 v, <15 pf, standard drive ? 16 ? ps s2:s1 = 1:0 mode, 3.3 v, <15 pf, high drive ? 14 ? ps s2:s1 = 1:0 mode, 2.5 v, <15 pf, standard drive ? 23 ? ps s2:s1 = 1:0 mode, 2.5 v, <15 pf, high drive ? 22 ? ps t per [10,11] period jitter, peak 3.3 v supply, 66?100 mhz, <15 pf ? 20 75 ps 3.3 v supply, >100 mhz, <15 pf ? 15 45 ps 3.3 v supply, >66 mhz, <30 pf, standard drive ? 40 100 ps 3.3 v supply, >66 mhz, <30 pf, high drive ? 30 70 ps 2.5 v supply, >66 mhz, <15 pf, standard drive ? 25 60 ps 2.5 v supply, 66?100 mhz, <15 pf, high drive ? 25 60 ps 2.5 v supply, >100 mhz, <15 pf, high drive ? 15 45 ps s2:s1 = 1:0 mode, 3.3 v, <15 pf, standard drive ? 28 ? ps s2:s1 = 1:0 mode, 3.3 v, <15 pf, high drive ? 24 ? ps s2:s1 = 1:0 mode, 2.5 v, <15 pf, standard drive ? 40 ? ps s2:s1 = 1:0 mode, 2.5 v, <15 pf, high drive ? 37 ? ps notes 10. parameter is guaranteed by design and char acterization. not 100% tested in production. 11. typical jitter is measured at 3.3 v or 2.5 v, 29 c, with all outputs driven into the maximum specified load. further inform ation regarding jitter specifications may be found in the application note ?understanding data sheet jitter specifications for cypress clock products.? 3.3 v and 2.5 v ac el ectrical specifications (continued) parameter description test conditions min typ max unit [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 8 of 17 switching waveforms test circuits duty cycle timing t 1 t 2 v dd /2 v dd /2 v dd /2 all outputs rise/fall time output t 3 3.3v(2.5v) 0v 0.8v(0.6v) 2.0v(1.8v) 2.0v(1.8v) 0.8v(0.6v) t 4 output-output skew t 5 output output v dd /2 v dd /2 input-output propagation delay v dd /2 t 6 input clkout v dd /2 v dd /2 v dd /2 t 7 any output, part 1 or 2 any output, part 1 or 2 part-part skew 0.1 ? f v dd 0.1 ? f v dd clk c load outputs gnd gnd test circuit # 1 [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 9 of 17 supplemental parametric information data is shown for 66 mhz. delay is a weak function of frequency. data is shown for 66 mhz. delay is a weak function of frequency. -1200 -1000 -800 -600 -400 -200 0 200 400 600 800 1000 1200 -20 -10 0 10 20 load clkout- load clka/b (pf) delay ref input to clka/b (ps) standard drive high drive figure 1. 2.5 v typical room temperature graph for ref input to clka/clkb delay versus loading difference between clkout and clka/clkb -1200 -1000 -800 -600 -400 -200 0 200 400 600 800 1000 1200 -20 -10 0 10 20 load clkout- load clka/b (pf) standard drive hi g h drive figure 2. 3.3 v typical room temperature graph for ref input to clka/clkb delay versus loading difference betwee clkout and clka/clkb [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 10 of 17 note that the 30-pf data above 100 mhz is beyond the data sheet specification of 22 pf. note that the 30-pf high-drive data above 100bmhz is beyond the data sheet specification of 22 pf. 25 50 75 100 125 150 175 200 33 66 100 133 166 200 233 frequency (mhz) 15pf, -45c, standard drive 15pf, 90c, standard drive 30pf, -45c, standard drive 30pf, 90c, standard drive 15pf, -45c, high drive 15pf, 90c, high drive 30pf, -45c, high drive 30 p f, 90c, hi g h drive figure 3. 3.6 v measured supply current versus frequency, drive strength, loading, and temperature 20 40 60 80 100 120 33 66 100 133 166 200 frequency (mhz) 15pf, -45c, standard drive 15pf, 90c, standard drive 15pf, -45c, high drive 15pf, 90c, high drive 30pf, -45c, high drive 30pf, 90c, high drive figure 4. 2.7 v measured supply current versus frequency, drive strength, loading, and temperature. [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 11 of 17 0 50 100 150 200 250 300 350 0 50 100 150 200 250 frequency (mhz) 15 pf, standard drive 15 pf, high drive 30 pf, standard drive 30 pf, hi g h drive figure 5. typical 3.3 v measured cycle-to-cycle jitter at 29 c, versus frequency, drive strength, and loading 0 50 100 150 200 250 300 350 0 20 40 60 80 100 120 140 160 180 200 frequency (mhz) 15 pf, standard drive 15 pf, high drive 30 pf, hi g h drive figure 6. typical 2.5 v measured cycle-to-cycle jitter at 29 c, versus frequency, drive strength, and loading 0 50 100 150 200 250 0 50 100 150 200 25 0 frequency (mhz) 15 pf, standard drive 15 pf, high drive 30 pf, standard drive 3 0 p f , h i g h drive figure 7. typical 3.3 v measured period jitter at 29 c, versus frequency, drive strength, and loading 0 50 100 150 200 250 0 50 100 150 200 250 frequency (mhz) 15 pf, standard drive 15 pf, high drive 30 pf, high drive figure 8. typical 2.5 v measured period jitter at 29 c, versus frequency, drive strength, and loading [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 12 of 17 note 12. typical jitter is measured at 3.3 v or 2.5 v, 29 c, with a ll outputs driven into the maximum specified load. further inform ation regarding jitter specifications may be found in the application note ?understanding data s heet jitter specifications for cypress clock products.? -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v, high drive 3.3v, standard drive 2.5v, standard drive 2.5v, high drive 2.5v, standard drive 2.5v, high drive -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 100 mhz 156.25 mhz 3.3v, high drive 2.5v, high drive 3.3v, standard drive 2.5v, standard drive -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v, high drive 3.3v, standard drive 2.5v, standard drive 2.5v, high drive 2.5v, standard drive 2.5v, high drive -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 100 mhz 156.25 mhz 3.3v, high drive 2.5v, high drive 3.3v, standard drive 2.5v, standard drive figure 9. typical phase-noise data at 100 mhz (top) and 156.25 mhz (bottom) across v dd and drive strength [12] [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 13 of 17 ordering code definition ordering information ordering code package type operating range lead-free cy23ep09sxc-1 16-pin 150-mil soic commercial cy23ep09sxc-1t 16-pin 150-mil soic ? tape and reel commercial cy23ep09sxi-1 16-pin 150-mil soic ? industrial CY23EP09SXI-1T 16-pin 150-mil soic ? tape and reel industrial cy23ep09sxc-1h 16-pin 150-mil soic commercial cy23ep09sxc-1ht 16-pin 150-mil soic ? tape and reel commercial cy23ep09sxi-1h 16-pin 150-mil soic industrial cy23ep09sxi-1ht 16-pin 150-mil soic ? tape and reel industrial cy23ep09zxc-1h 16-pin 4.4-mm tssop commercial cy23ep09zxc-1ht 16-pin 4.4-mm tssop ? tape and reel commercial cy23ep09zxi-1h 16-pin 4.4-mm tssop industrial cy23ep09zxi-1ht 16-pin 4.4-mm tssop ? tape and reel industrial cy company id: cy=cypress base device part number cy23ep09 = 9-output zero delay buffer temperature grade: i = industrial, c = commercial s(x) c 1 (h) output drive: 1=standard drive, 1h=high drive 23ep09 (t) package: s=soic, leaded z=tssop, leaded sx=soic, pb-free zx=tssop, pb-free tape and reel [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 14 of 17 package drawing and dimensions 16-lead (150-mil) soic s16 51-85068-*c 16-lead tssop 4.40 mm body z16.173 51-85091-*c [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 15 of 17 acronyms document conventions units of measure acronym description pci personal computer interconnect pll phase locked loop sdram synchronous dynamic random access memory soic small outline integrated circuit tssop thin small outline package zdb zero delay buffer symbol units of measure c degree celsius a micro amperes ma milli amperes ms milli seconds mhz mega hertz ns nano seconds pf pico farad ps pico seconds vvolts [+] feedback
cy23ep09 document #: 38-07760 rev. *c page 16 of 17 document history page document title: cy23ep09 2.5 v or 3.3 v, 10-220-mhz, low jitter, 9-output zero delay buffer document number: 38-07760 rev. ecn no. issue date orig. of change description of change ** 345446 see ecn rgl new data sheet *a 355777 see ecn rgl updated part to part skew to agree with latest char results *b 401036 see ecn rgl added pll-bypass jitter added phase-noise graph added 2.5v delay vs. load graph removed preliminary *c 3270178 06/01/2011 bash updated as per template updated package diagram 51-85068 and 51-85091. added acronyms and units of measure table [+] feedback
document #: 38-07760 rev. *c revised june 1, 2011 page 17 of 17 all products and company names mentioned in this document may be the trademarks of their respective holders. cy23ep09 ? cypress semiconductor corporation, 2010-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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